Unfortunately, the Perfmon counters of the #Intel #NovaLake INT cluster inherited the grouped nature from the older *Coves with a central scheduler, so the number of ports used here is unknown (except for the 3 JEUs).

A new feature was mentioned for #Intel #CoralRapids on the Linux kernel mailing list: APIC timer virtualization lore.kernel.org/lkml/amnPFlS...

#AMD -- desktop #OlympicRidge CPUID is B80F80 -- mobile #Medusa2 CPUID is BE0F00 lore.kernel.org/platform-dri...

#AMD refreshed the "AMD64 Architecture Programmer's Manual, Volumes 1-5" 40332 to 4.10, all-in-one: Vol1 24592-Rev. 3.25-May 2026 Vol2 24593-Rev. 3.45-Jul 2026 Vol3 24594-Rev. 3.38-Jul 2026 Vol4 26568-Rev. 3.27-Jul 2026 Vol5 26569-Rev. 3.16-Nov 2021 docs.amd.com/v/u/en-US/40...

My attempt to assign CCD types on 6th Gen #AMD #EPYC SKUs #Zen6 #Monarch #Powderhorn #Morpheus

Until the 84-core #AMD #Sorano #EPYC 8635P came to mind (12 CCD x 7-core), this 176-core (8 CCD x 22-core) #Zen6c seemed completely incomprehensible without a 3rd CCD type. But supposing 11x3 core within the #Monarch CCD makes this a yield optimization. blogs.microsoft.com/blog/2026/07...

#Intel XED got #ACE (AI Compute Extensions) of x86 Ecosystem Advisory Group support: github.com/intelxed/xed... #ACE specification: x86ecosystem.org/wp-content/u... #ACE1 #AVX10_V2_AUX

CPUID.1Ah.EAX: 20000000: #Tremont 20000001: #Gracemont 20000002: #Crestmont 20000003: #Skymont 20000004: #Darkmont 20000005: #ArcticWolf 40000000: #SunnyCove 40000001: #GoldenCove 40000002: #RedwoodCove 40000003: #LionCove 40000004: #CougarCove 40000005: #CoyoteCove GitHub github.com/intel/perfmo...

#Intel perf tool got #NovaLake CPUID 300F10 300F30 support: According to this commit, while the #ArcticWolf config is quite similar to #Skymont / #Darkmont (8 INT+4 FP, FP probably 128b->256b), the #CoyoteCove FP has increased to 6 ports from 4 in #LionCove / #CougarCove. github.com/intel/perfmo...

Another interesting GCC patch: disabling the memory-form of NDD #Intel #APX instructions. #DiamondRapids is not mentioned, perhaps this is an #ArcticWolf related issue? i386: Add tuning to disable memory-form NDD gcc.gnu.org/git/?p=gcc.g...

#AMD refreshed the "AMD64 Flexible Return and Event Delivery (FRED) Virtualization" 69191 to v1.10 pdf: docs.amd.com/v/u/en-US/69... #FRED #Zen6 #Venice #Verano

An interesting #APX GCC patch: i386: Disable SETcc.ZU generation on DMR/NVL via tune flag gcc.gnu.org/git/?p=gcc.g... Strange, isn't a 6 byte EVEX better than a 2/3/4 byte XOR + 3/4 byte SETcc? #DiamondRapids #NovaLake #PantherCove

the goal is certainly to disable #Intel CPU detection (and execution of specific code paths). x.com/sh0dan/statu...

According to this Linux kernel patch, the #AMD LP-core is clearly marked in the CPUID: CPUID.80000026h.EBX[31:28]=2 #Zen6LP lore.kernel.org/linux-acpi/2...

#Intel released the 62nd edition of the ISA Extensions Reference with. #UTMR and #AMX_TF32 support removed (it means only one instruction: TMMULTF32PS) Download: cdrdv2-public.intel.com/922690/31943... #DiamondRapids #NovaLake #PantherCove #CoyoteCove #ArcticWolf

This GCC patch reveals that the #Hygon CPUID 900F80 is Suzhou, and supports #AVX512 up to #AVX512_VP2INTERSECT (= #AMD #Zen5 level) github.com/gcc-mirror/g...

This microcode update reveals the first #PantherLakeR stepping: CPUID E0652 winraid.level1techs.com/t/intel-amd-...

I was wrong. According to this #AMD #Venice patch, #Zen6 's VNNI_INT8 capabilities are also supposedly better than #Zen5 's. github.com/amd/aocl-dlp...

Visualized #AMD #Zen5 #ThreadripperPro 9000WX topology: www.instagram.com/p/DZ31Gu_FwT... www.instagram.com/p/DZ31Gu_FwT... On AMD.com : www.amd.com/en/products/...

#Intel released the 92nd edition of the Software Developer’s Manuals with fixes and clarifications: All-in-One: cdrdv2-public.intel.com/922475/32546... Changes v084: cdrdv2-public.intel.com/922474/25204...

Strange. #AMD's documentation page lists both #SP7 and #SP8 's embedded #Zen6 #EPYC as 9006 instead of 11006/10006 (or B006/A006 if they've switched to the more practical hex notation). docs.amd.com/search/all?v...

A good summary: x86ecosystem.org/resource/ai-...

The x86 Ecosystem Advisory Group released the #ACE (AI Compute Extensions) specification v1.15: x86ecosystem.org/wp-content/u... #EAG #Intel #AMD #Zen7 #CoralRapids #AVX512 #AVX10 #AMX

These pages reveal some details about the #AMD #Zen6-based #ThreadripperPro: CPUID BA0F80, #MustangPeak codename, #TR6 socket, TSMC 2-nm cores with DDR5 and PCIe Gen 6 support docs.amd.com/v/u/en-US/ug... docs.amd.com/v/u/en-US/ug...

New #Intel #GraniteRapidsSP SKU: #Xeon 6503P (8c, 48MB L3): Ark: www.intel.com/content/www/... Presentation: www.intel.com/content/www/...

Nothing important here, just good to see #Intel client CPUs back in the #AVX512 arena: lore.kernel.org/lkml/2026061...

#Intel refreshed the "Intel Architecture Memory Protections for Confidential Computing" Technical Paper 869103 pdf: cdrdv2-public.intel.com/869103/2026%...

#Intel released the 7th edition of the "Intel® Architecture Memory Encryption Technologies" pdf v1.7 336907 cdrdv2-public.intel.com/854686/33690... #TME #TME_MK

#AMD #EPYC 9005 BIOS & Workload Tuning Guide 58467 2.2 pdf #Zen5 #Turin docs.amd.com/v/u/en-US/58...

#Intel projects 2026+ v081: - Clearwater Forest Brand name is Xeon 6900E+, source [52] - Diamond Rapids launch date is 2027 - Diamond Rapids up to 192 core, source [53] - Coral Rapids 128 / 320 cores, source [54] GitHub: github.com/InstLatx64/I... 2/1