Greg
@gregdavill
Electronics engineer. RISC-V ASICs at IQonIC Works 🧙♂️ (He/Him) I also take macro photos of electronics
I fixed a damaged USB-A port on a PS5 this week. The most tedious part was the 42 security trox screws encasing an EMI/Heat shield to the motherboard. 🙃
Not my neatest work, but it works. This wire's pvc melts super quickly, so soldering can be a challenge. But I still prefer having the colours 🙂 A quick 3d print to hold the wires avoids strain
The scope traces were crisp atleast. Maybe I didn't need to look to closely at my xacto scratching and probe landing 😆
Pretty cool that you can actually see the logic clouds as a blob in the middle. Early parts from wafer.space, perfect to take photos
Quick weekend project to put enclosures over my various Glasgow prototypes. Teaching myself the "configurations" feature in fusion to handle slightly component placement differences between various Cx versions.
First samples on the first run from wafer.space! There is a disclaimer with these parts, that only ~80% are fully bonded successfully. This could be marketed as a feature, an air gapped solution using state of the art wireless bond wires. 😜
Fresh and custom silicon day! 😍 This is a multicore riscv soc design based on the serv processor core. Based on GF180MCU PDK, and fabricated through wafer.space 🚀
LEDs ❇️ These are about all on at about the perfect brightness for visual indication. But my standard macro photography process (off camera flash) just floods so much extra light that these appear really dim.
Some BGA footprints are distinct enough to act like a fingerprint for the part. If you've used this part on a board design before you'll likely recognise it. 😉
Now all my benchtop gear that had GPIB can now connect via USB 🙌 "Weekend" project complete!
Printed off some enclosures. Made a small modification around the M3 nut tolerances, which was easy as the f3d file was provided in the repo 👍
It's not stupid if it works 😅 Avoiding soldering down a connector for the one time operation of burning fuses, and loading bootloader/firmware for some UsbGpib adapters. github.com/xyphro/UsbGpib
I'd forgotten that the ECP5-25F doesn't have all the I/O, and 4 or so pins that are on the 45/85F are N/C on the 25F. I just happened to use one of these for the ULPI interface. 🥲 Bodge wire to the rescue! Now we're enumerating again! USB boot loader in gateware, takes up ~15% of the device
These two boards have the same BGA geometry defined in their gerbers. For some reason JLCs DFM adjustments have expanded all the "via in pad" connections. Makes for an interesting visual effect.
The bodge works! A DFF in front of the ECP5's FPGA SPI configuration port before a mix leading to FLASH and PSRAM. Enabling an initial jump through FLASH where the clock frequency is bumped and QSPI entered. This now fixes an issue violating the PSRAM's tCE<8us requirement.
Plan vs. Execution The messier the plan the cleaner the bodge looks in comparison. 😅
Can't recall where this came from, but ended up in my labs cable drawer. Curious why it wouldn't enumerate.. 🤮