Jan Gray

@jangray

Kilocore RISC-V FPGA accelerators; former Microsoft dev tools architect; RISC-V SoftCPU SIG & Composable Custom Extensions Task Group; blog: . Cyclist. Let's try kindness. 🇨🇦-🇺🇸

1.444 Folgt1.221 Follower1.314 Posts

Bluesky

Ist das dein Profil?Übernimm es — dann gehört dir jangray.dirty.social.Profil übernehmen

Jan Gray@jangray· 1d

Jan Gray@jangray· 1d

#FPGA UCIe chiplets a new era of modularity, heterogeneity, and domain specialization.

Slide from Hot Chips, introducing Versal RF’s UCIe chiplets interfaces.

Jan Gray@jangray· 2d

#HotChips ZFLOPS/100MW, a bold new hyperbole unit for the "AI Factory" (unfortunate term)

Table in an NVIDIA Rubin slide:
Specification 100 MW AI Factory*
NVFP4 Inference 2 ZFLOPS
NVFP4 Training 1.4 ZFLOPS
HBM4 Memory 11 PB
HBM4 Memory Bandwidth 800 PB/s

Jan Gray@jangray· 3d

#FPGA #HotChips #OoO #EDGE This just came up again. Good times! arxiv.org/pdf/1803.06617

Floorplan of an FPGA-efficient “parallel” OoO instruction scheduler.

Floorplan of an FPGA-efficient OoO instruction window including teo “incremental” dataflow instruction schedulers.

Jan Gray@jangray· 8d

All human knowledge, circa 1986

Book cover what they teach you at Harvard business school and book cover what they don’t teach you at Harvard business school

Jan Gray@jangray· 22d

zNAND-O: “the first step toward high bandwidth flash” … “From 2028, zNAND-O will drive your AI innovation.

Jan Gray@jangray· 22d

Here at #FMS2026 Samsung, going beyond 2.5D HBM4e/5, discloses future 3D zHBM and zNAND-O. zHBM: You knew it was inevitable. IMO this 3D integration will require a tour de force of packaging and codesign to match the pitches of the SoCs x stacks and cope with all the power and thermal challenges.

Samsung slide titled rethinking HBM for HBM stats directly atop the XPU

Samsung slide illustrating one zHBM stack on XPU, providing an advocate 4-8 times the bandwidth, 3 times the perf/Watt vs HBM.

Samsung slide titled ultra high performance, subtitle wafer on wafer integration and hybrid copper bonding realize ultra high density TSVs and ultra high performance.

Samsung slide titled overcoming the thermal challenge, subtitled thermal performance is secured through optimized stack height, and optimized metal layers

Jan Gray@jangray· 24d

“Or, if belonging to a publishing house isn't what the members of ACM envision, then it is time to ask what ACM must do to become a professional organization again.”

Jan Gray@jangray· 24d

Worthy of your attention is this editorial from CACM Editor-in-Chief @jameslarus.bsky.social on, I think, the soul and purpose of ACM. cacm.acm.org/opinion/with... Jim nails my reasons for first joining ACM 40 years ago, how it changed, its future as a professional society. (Lifetime member.)

‘I was excited to "advance the science, development, construction, and application of the new machinery for computing, reasoning, and other handling of information" (ACM's original mission), so I joined the computing profession's professional society. It didn't hurt that students paid a small fee and received a large amount of printed technical material, but I joined because I felt ACM represented the computing profession that I wanted to be part of.’
— James Larus, in “Wither ACM? Publish and Perish? (ACM has shifted from a professional society for the academic computing community to a professional publisher).”, https://cacm.acm.org/opinion/wither-acm-publish-and-perish/

Jan Gray@jangray· Jul 27

“There are fewer rules than you think.” - Linda Carson

Linda Carson’s tattoo, reading
“Only do what only you can do.” — E.W. Dijkstra

Jan Gray@jangray· Jul 7

Now when it (invariably) drifts I just write "Dijkstra rule!"

CLAUDE life:

## Spec & comment concision (load-bearing rule)

Apply three checks to every spec paragraph and source comment before
keeping it:
- **Load-bearing:** deletion costs the reader something they can't get
from the cited §.
- **Unique:** not paraphrasing prose that lives elsewhere.
- **Current:** about now — not "will"/"may"/hypothetical future, and
not "no longer"/"instead of" narration of past states.

Fail any check → delete or shorten. Default source comment is one
line; more than three is a smell. Cite, don't restate.

Specs and docs state the current truth as positive invariants;
evolution belongs in the change log at the bottom of the spec.

Register: precise, meticulous, concise. The audience is an expert
computer architect (see methodology step 3). Standard terms of art
only — no slang, colloquialisms, or conversational informality leaking
from the session into artifacts. Every quantity cited or marked TBD;
never invented.

This rule is load-bearing because the failure mode is chronic: verbose
prose and uncited numbers creep back. Write every artifact sentence as
if the famously meticulous Prof. Dijkstra will review it.

Jan Gray@jangray· Jul 4

🎶 Saturday in the park I think it was the Fourth of July Saturday in the park I think it was the Fourth of July People dancing, people laughing A man selling ice cream Singing Italian songs 🎶 Great day for a Blue Jays / Mariners game. The old expansion teams rivalry! … oh.

Jan Gray@jangray· Jun 30

#FPGA As we bid a fond farewell to FPGAs with HBM today, killed by AI -- AMD launches Versal Premium gen2 with 32 GB LPDDRX memory on package, much as predicted. www.amd.com/en/products/... Coming soon -- ~60% of the DRAM bandwidth of 2019 Virtex UltraScale+ HBM(2), ~35% of 2023 Versal HBM(2e).

Render of a Versal Premium gen2, with FPGA die and four LPDDR5Xs

Jan Gray@jangray· Jun 18

#FPGA #RISCV Reinventing the wheel, I wrote a frugal 32b/64b RISC-V compliant div/rem, early out, nonrestoring radix-2 divider. * 32b: 640 MHz, 155 LUTs, 14-36 cycles * 64b: 520 MHz, 289 LUTs, 22-68 cycles (UltraScale+ -1 fabric) Per Jan's Razor, planning to share one div/rem unit per 2-4 PEs.

Vivado device view of a critical path in a fast frugal 32b divider.

Jan Gray@jangray· Jun 16

#FPGA Welcome AMD Spartan UltraScale+ SU200P, “entering volume production in July 2026“! 100K 6-LUTs 2 MB of UltraRAM. Much faster fabric. Hard LPDDR5 controllers. Etc. The best new Spartan FPGA in ages. Oh the fun we’re going to have.

Table from press release:
What's Inside the AMD Spartan UltraScale+ SU200P FPGA
Capability
SU200P FPGA
System logic cells
218,000
1.OV - 3.3V I/O
Up to 572, 3.2 Gb/s MIPI
Block RAM / UltraRAM
6.8 Mb / 18.0 Mb
GTH transceivers
Up to 8 × 16.3 Gb/s
PCle® hard IP
Gen4 x8
Hard memory controllers
LPDDR4X / LPDDR5 / LPDDR5X up to 4,266 Mb/s
Lifecycle
2045+

Jan Gray@jangray· Jun 10

#FPGA Did you know? Beside LUT inputs (W)ADR[5:0], UltraScale LUTRAM have 3 write-port address decoder inputs WADR[8:6] usable to build deeper LUTRAM arrays and for the funky RAM64X8SW, using the RAMS64E1 configured with WA[789]USED=1.

Primitive RAM64X8SW "64x6b RAM w/ single-bit write!" from UG974

Vivado device view of instantiation of one LUT in one RAM64X8SW. Here we see the LUT has 3 additional address lines WADR6,7,8 used to selectively enable writes to this RAM bit among the 8 bits, at no additional cost.

Jan Gray@jangray· May 31

As a teenager I had the help of kind @waterloomath.bsky.social CS students coaching me. “I’ll never afford <8b PC>!” “Well — build your own. Here’s the Motorola databook, the TTL databook, BYTE/Ciarcia. We’ll go to the chip stores (College & Spadina, Queen & Spadina). You’ll need an OK WSU-30M …”

The indispensable OK WSU-30M hand wire wrap tool. Still sold. “An elegant weapon for a more civilized age.”

Jan Gray@jangray· May 11

Well thank you and Vickie and your friends, I loved reading that back in the day.

Program from Before the Dawn and the ninth wave poem on crepe paper,
Wave after wave, each mightier than the last, …

Jan Gray@jangray· May 9

My new macro placer, places.

Some nondescript FPGA datapath, viewed in Vivado device view, zoomed way-in, to show two fully utilized CLBs and their INT routing tile

Jan Gray@jangray· May 9

:-)

Some kind of nondescript floorplanned FPGA circuit!

Jan Gray@jangray· May 5

#FPGA XCSU200P: gray: 240Rx52C slices = 100K LUTs green: 64 URAM = 2 MB yellow: 48x4 BRAM = 768 KB blue: 96x4 DSP= 384 DSPs magenta: 2 HSMs/LPDDRMCs: ~34 GB/s (?) / 132 IOs red: 8 GTHs = 8@16.3 Gb/s = 130 Gb/s reddish: 336 HD + 104 HP IOs white: 2 PCIE4CEs = 1x PCIe gen4x8 or 2x gen4x4 purple: AMS?

A colored die plot of an XCSU200P Spartan UltraScale+ 200 FPGA:
gray: 240Rx52C slices = 100K LUTs
green: 64 URAM = 2 MB
yellow: 48x4 BRAM = 768 KB
blue: 96x4 DSP= 384 DSPs
magenta: 2 HSMs/LPDDRMCs: ~34 GB/s (?) / 132 IOs
red: 8 GTHs = 8@16.3 Gb/s = 130 Gb/s
reddish: 336 HD + 104 HP IOs
white: 2 PCIE4CEs = 1x PCIe gen4x8 or 2x gen4x4
purple: AMS?

Jan Gray@jangray· May 1

APL Vade Mecum (Ken Iverson) via: APL in your pocket: Reprinting Canadian computing history www.uvic.ca/library/abou... Thanks @robferguson.bsky.social

APL vade mecum — concise printed business card sized summary of the language and its menagerie of operators and semantics

Jan Gray@jangray· May 1

www.uvic.ca/library/abou... hcl.library.uvic.ca Good on you @robferguson.bsky.social

Quote from the article:
"My hope is to engage computer science students, and even art students, with the history of their field. And also to make sure that these machines are preserved in a way that is publicly accessible, and sustainable over time. Even if I preserve them, I'm not going to have the resources or the ability to keep them running forever, and having them stored in somebody's basement is not really serving the public good." - Rob Ferguson

Jan Gray@jangray· Apr 30

Epilog: LUT6_2 will return! Thanks AMD. They're good folks.

AMD states: "These [LUT6_2] will be added back to userguide in the next vivado major release. Untill then you can use it from the Language templates."

Jan Gray@jangray· Apr 2

It’s great to learn that MPR rolls on. Reporting from the Golden Age of RISC, here as chronicled by Michael Slater’s Microprocessor Report roll up in the book “Understanding RISC Processors” 👇

TOC from Understanding RISC Microprocessors
Perspective
August, 88)
(February, '89)..
Microprocessor Architectures in the 1990s.
ACE Defines MIPS/Intel Platform (May 1, '91)..
Viewpoint: MIPS and Sunset (June 26, '91).
December 18, '91).
(December 26, '91)...
Viewpoint: Die Like a Man (May 6, '92)...
The Editor's View: Pocket Intelligence-The Next Killer Application (July 8, '92)
1-72
Viewpoint: Architecture vs. Implementation in RISC Wars, by John H. Wharton
..1-1
Tredennick Presents the Case for CISC (November, '88)..
1-3
Viewpoint: It's Not RISC vs. CISC, It's New vs. Old, by Nick Tredennick

..1-5

1-10
Microprocessors for Embedded Control (February 7, '90).
1-15
Viewpoint: Another Look at Architectures in the 1990s (February 21, 90).
1-19
Viewpoint: What is RISC?-One Last Time (April 18, '90)..
1-21
Viewpoint: It Doesn't Have to be RISC to be Good (June 20, '90)..
1-22
Design Issues for Next-Generation Processors (September 19, '90).
1-24
The Editor's View: The Coming Embedded Control Bloodbath (October 31, '90)..
1-30
Personal Views on the Future of Microprocessors (November 7, '90)..
1-31
Viewpoint: 1991: The Year of the RISC (February 6, 91).
1-35
1-38
The Editor's View: Is 64 Bits the Next Step? (March 6, '91).
The Editor's View: Superpipelining, Superscalar, and Superhype (April 17, '91).
1-39

1-40

Viewpoint: A Vision of ACE and the Future of Intel May 29, 91)..
1-45
1-47
Can the 386 Architecture Keep Up? (December 4, 91) ..
1-53

Embedded 32-Bit Processors Add Flash Memory, On-Chip Peripherals
1-59
The Editor's View: SPARC, MIPS, Power PC Lead Race for Desktop RISC

1-61
1-62
Embedded Processors Focus on Integration (January 22, '92)..
The Editor's View: Computer Makers Lead in High-End Processors (February 12,

TOC
Perspective (continued)
The Editor's View: Personal Communicators— Almost Here? (July 29, '92)...
Windows NT Establishes New PC Platforms (August 19, '92)....
Viewpoint: CISCs are Not RISCs, and Not Converging Either (March 25, '92).
Oblique Perspective: Why RISC is Doomed (August 19, '92)...
Viewpoint: Escape from the Temple of Doom (September 16, '92).
Superscalar Scorecard: Who's On First? (October 7, '92)...
The Editor's View: RISCs Adjust Course Downward (October 28, '92)..
Microprocessor Development Beyond 1995 (December 9, '92).. 1992 in Review: The Top RISC Processors (December 30, 92).
Editorial: So Where's the Shakeout? (December 30, '92)...
Editorial: Speed Kills? Not for RISC Processors (March 8, '93)
Comparing the New 64-Bit RISCs (March 8, '93)..
Intel 80960
Intel Reveals Register Scoreboarding at ISSCC (March 88)
Intel Unveils Radical New CPU Family (April '88)...
Intel 80960 Attacks Drawbacks of Prior RISCs (May '88).
An Insider's View of the 80960 Architecture (October '88)
Intel Previews Superscalar 960 CPU (May '89).....
Intel 80960CA Breaks IPC Barrier (September '89)..
Obituary: Intel and Siemens Pull the Plug on BiN (October '89)...
Conflict Avoidance Key to Superscalar Efficiency (November '89)
Intel and AMD Battle Over Processor Benchmarks (December '89).
Intel Adds Low-End, High-End 960 Processors (October 17, '90)..
Motorola 88000
Motorola 88000 RISC Chip Set Emerges (May '88).....
Motorola 88200 CMMU Supports Multiprocessing (June '88)...
Data General Unveils ECL 88000 Design (May '89)....
88000 Gains Ground in RISC Processor Battle (August 89)
Motorola Reveals 88000 Strategy (November 7, '90)....
1-73
1-74
1-76
... 1-81
1-85
...1-88
1-94
1-95
1-98
1-103
1-104
1-105
...2-1
...2-5
.. 2-11
.. 2-15
.. 2-17
2-18
2.25
2-27
2-31
2-33
...3-1
....3-7
.....3-9
..3-10
3.12
SPARC
Cypress SPARC Chips Target Workstations (July "88)..
SPARC Support Multiples: I Aligns with Cypress, LST Covers all Bases (September '88)....
Fujitsu Announces SPARC Sup…

Formally Unveils Long-Awaited 29050 (October 3, '90).

AMD's 29030 "Lynx" Reduces System Cost (May 15, '91)
5-13
5-17

AMD's 29200 Aims At Low-Cost Laser Printers (November 20, 91).
5-21
MIPS
Mips Challenges SPARC and the 88000 (February '89)..

System Design with the MIPS R3000 (March '89)...
..6-1
Mips Acknowledges Three Minor Bugs in R3000 (August '89).
....6-8
IDT Reveals First R3000 Derivative (November '89).
6-13
6-14
MIPS Chip Set Implements Full ECL CPU (December'89)..
6-16
ECL Bus Controller Hits 266 Mbytes/s (January 24, 90).
6-23
LSI Logic Announces First MIPS System Chip Set (July 18, '90)..........
6-26
The Editor's View: The Fate of ECL Microprocessors (September 5, '90).
... 6-30
IDT Introduces Embedded MIPS Processors (October 3, 90) ...
....6-31
MIPS-Based Processor Provides High Integration (October 31, '90).
.. 6-35
MIPS Previews 64-Bit R4000 Architectue (February 6, '91).
6-39
Performance Semi Adds Integrated MIPS Chip (September 18, '91.
... 6-45
MIPS R4000 Sets Performance Record (October 2, '91)..
6-49
R4000 Extends R3000 Architecture with 64-Bit Capabilities (October 16, '91)..
.... 6-56
LSI Creates Single-Chip X Terminal Controller (October 30, '91)...
.... 6-60
Mips Releases R4000 Errata List (October 30, '91)..
... 6-63
IDT's R3081 Adds FPU, Larger Cache to R3052 (January 22, '92)....
.. 6-65
MIPS and Silicon Graphics Merge (March 25, '92)..
.. 6-68
The Editor's View: What Happened to MIPS? (April 15, '92).
6-71
MIPS Lays Out R4000 Roadmap (April 15, '92)....
6-72
MIPS Announces First ARC Systems (May 6, '92).
6-73
MIPS R4400 Offers 60-80% Performance Boost (November 18, '92)..
6-79
New MIPS Chip Targets Windows NT Boxes (November 18, '92).
6-81
IDT R3041 Lowers Embedded MIPS Entry Cost (November 18, '92)..
... 6-83
SGI Provides Overview of TFP CPU (February 15, '93).
....
6-85
Intel i860

Intel's i860 Sets New Performance Standard (March '89)...
....7-1
Viewpoint: Unanswered Questions on the i860 (March '89)..
... 7-8
Evaluating the i860…

DEC Alpha
DEC Enters Microprocessor Business with Alpha (March 4, '92).
DEC's Alpha Architecture Premiers (March 4, '92)..
Digital Plans Broad Alpha Processor Family (November 18, '92).
Hobbit
AT&T Sampling Low-Power "Hobbit" Processor (February 12, '92).
Hobbit Enables Personal Communicators (October 28, '92).
EO Announces First Personal Communicator (November 18, '92)
Miscellaneous
Philips Gives LIFE to VLI (August 6, '90)..
Zilog Licenses Hyperstone as Core Processor (September 19, '90).
National Unveils Superscalar RISC Processor (February 20, '91)..
Transputer Provides MP Building Block (April17, '91)..
T-9000 Boosts Transputer Performance (May 15, '91).
Microprocessors Displace DRAMs at Forefront of ISSCC (March 25, 92).
T9000 Transputer Begins Sampling (April 19, '93).

Jan Gray@jangray· Mar 31

Will there be a Hall of Space in the 2029 OSC-lite Cake on the Lake? What has become of the magnificent Apollo Saturn V / launch tower display abruptly removed from the OSC Tower Building?

From “Tour Ontario Science Centre”,
Photo 1, a guest is sitting in the hatch of a Mercury capsule.
Photo 2, model of Apollo Saturn V and launch tower, model of Apollo command module w/ astronauts, Alouette communications satellite.

Photo 1 of 3 space-suited astronauts on their backs in their Apollo 11 command module replica

Photo 2 of scale model of LEM and astronaut on the lunar surface.

Text block: “Explore the highest achievement of pure science and technology - the conquest of space! The entire Apollo moon landing program unfolds before you... the 20-layered space suits, the life-giving garments designed to withstand a 500 degree temperature range, astronauts' food packs, the quarters shared by the pioneers of space. Climb into a space capsule and experience the separation from the Lunar Excursion Module - the 180 degree rotation to dock with it... manoeuvers made by the astronauts. All the sounds of space to earth communication surround you. You're out of your world!”

Jan Gray@jangray· Mar 29

@kccclaudia.bsky.social Saw you on YT this morning, and in person this afternoon. Thank you for all you do. Looking forward to riding the 2 line all about.

Boromir says:
One does not simply go to Seattle!
But now we can — now we must!

Jan Gray@jangray· Mar 27

From 2016 😀

Diagram of a CMOS NAND gate — two N FETs in series pulling down to ground, two P FETs in parallel pulling up to Vdd

At the (green) blackboard illustrating a NAND gate

At the white board, a fancier 2-input XOR gate implement from 3 inverters and two NAND gates.

Jan Gray@jangray· Mar 25

👍

Synopsis of April 5, 2018 episode of In our Time:

“Melvyn Bragg and guests discuss the role of slavery in the Roman world, from its early conquests to the fall of the Western Empire.
The system became so entrenched that no-one appeared to question it, following Aristotle's view that slavery was a natural state. Whole populations could be marched into slavery after military conquests, and the freedom that Roman citizens prized for themselves, even in poverty, was partly defined by how it contrasted with enslavement. Slaves could be killed or tortured with impunity, yet they could be given great responsibility and, once freed, use their contacts to earn fortunes…”

Jan Gray@jangray· Mar 4

Sigh.