Testing CPU control of the Earthrise graphics engine. Open source designs running on an ECP5 #FPGA.

The Earthrise drawing engine assembler now outputs memory offsets and the mnemonics assembled. The drawing engine uses 16-bit instructions, but a 32-bit bus to match the 32-bit RISC-V CPU. While I'm big endian at (68K) heart, Earthrise is little endian to match RISC-V.

Oh no, there's a translation bug in my hardware 2D drawing engine... wait no, my docs aren't clear enough (even to me). Translation only affects coordinates set *after*. 😮‍💨 Docs revised. Now I can move onto CPU controlled animation testing.

Done a bit of work on the 🏝️ Isle.Computer graphics devices today. Here's a 16 colour compositor test running under simulation. #FPGA

It’s raining! 🌧️ It’s been so long, I’ve almost forgotten what rain is. Europe is very dry this summer.

🏝️ Isle.Computer doesn't have interrupts yet, but catching bus faults is still handy, especially when running software under Verilator simulation. Here's the code I worked on this morning. #FPGA

One courgette on the allotment managed to hide amongst the leaves.

I try to learn from past hardware, but I have to wonder what Sega were thinking with the Saturn architecture. Just look at the motherboard! I don’t envy game devs starting out with it. www.copetti.org/writings/con...

Think before you buy that dried fruit. #lego

Goodbye Radio 4 on Long Wave; on air for the last time today! www.bbc.co.uk/reception/wo...

My office aircon. 🥵

A first successful test for hardware scrolling, showing vertical and horizontal wrapping of my latency test image. You can see the four corners of the bitmap meeting in the bottom right of this capture. #FPGA

🏝️Isle.Computer now supports arbitrary bitmap canvas sizes: github.com/projf/isle/b... Not too exciting on its own, but it makes it much easier to support multiple resolutions and hardware scrolling. #FPGA

Looking promising. Here the #riscv CPU is updating the text scrolling register. There’s CDC from system to pixel clock domain. #FPGAFriday

Well, it works in simulation with one clock domain. But will 🏝️ Isle.Computer hardware registers work on real hardware with two clock domains? 🤔 #FPGA

Yikes. .io is expensive these days. But I’d be sad to retire projectf.io.

AMD (Xilinx) are no longer supporting Linux in the free version of #Vivado. You need to pay at least $1200/year! www.amd.com/en/products/... This makes no sense to me. This will make it harder for people to learn and get into #FPGA. 🤔

I just voted 🗳️ in the Hastings and East Sussex #elections.

Made some time for 🏝️ Isle.Computer today. Getting the graphics registers working across clock domains so the CPU can double buffer, scroll, adjust transparency etc. #FPGA Images show RISC-V CPU reading graphics registers in sim and on #ULX3S.

Just when you thought GPU pricing had lost the ability to shock. A mobile 5070 for £1150! 😮

French bram is on another level. #fpga

Sometimes the wrong palette turns out right.

Verilog error message of the day: "Illegal character in binary constant: 2". Yes, I'm appalled at myself too.

The drawing engine refactor was getting chunky, so I merged it. If you want to have a play, there are a few (not enough) details on the 🏝️ Isle.Computer blog: projectf.io/isle/2d-draw... This refactor will allow me to share vram between CPU and drawing engine for the first Isle release. #FPGA

Adding an enable signal to 🏝️ Isle.Computer drawing engine was more of a pain than I expected, but we're now ready to share vram access with the CPU. On the plus side, this also allows you to slow the action down so you can see the drawing happen. #FPGA #verilog

I've just updated 🏝️Isle chapter 6 software. It's exciting to work on big designs and graphics engines, but building a usable computer is about the small things too. #FPGAFriday github.com/projf/isle/t...

You can find the source code on GitHub (I'm considering moving to Codeberg): github.com/projf/isle Includes everything you need for: * Machdyne Lakritz (Lattice ECP5) * @digilent.bsky.social Nexys Video (Xilinx XC7) * Radiona #ULX3S (ECP5) * Verilator simulator with SDL (Linux/macOS/Windows)

Sometimes you need to ship it and call it a night, so I give you 🏝️ Isle.Computer Chapter 6 - Input Output: projectf.io/isle/input-o... Adds input hardware, uart, Isle edition of FemtoRV "Gracilis" RV32IMC CPU, software library in #riscv asm, Verilator/SDL sim improvements... #FPGA

Macintosh memory is so expensive. systemtalk.org/post/macinto...

Tired of Teams? Meet Macintosh style from 1985 with VMCO. I wonder if this could be ported to #GlobalTalk? 🤔 systemtalk.org/post/macinto...